Monday, October 13, 2008 |
7:30-8:45 | Registration |
8:40-9:00 | Welcome, Dimitrios Soudris, General Chair, Christian Piguet and Thanos Stouraitis, Program Co-Chairs |
9:00-10:00 | Keynote Talk: “Interconnect-Based Design Challenges in High Performance Three-Dimensional Circuits”
Eby G. Friedman, University of Rochester, USA |
10:00-10:30 | Coffee Break | |
10:30-12:00 | Lecture Room 1 | Lecture Room 2 |
| Session M1A: Analog Circuit Design
Chair: Alkis Hatzopoulos, Aristotle Univ. of Thessaloniki, Greece M1A-1: "An Improved, Accurate Charge Pump for Telecommunication Applications"
Vassilis Kalenteridis, Konstantinos Papathanasiou and Stylianos Siskos
M1A-2: "Analysis of Bang-bang CDR circuits with Equations of Linear Motion"
Archit Joshi
M1A-3: "Low-Voltage Bulk-Driven Fully Balanced Differential Opamp"
George Raikos and Spyridon Vlassis M1A-4: "Non Inverting Voltage Amplifier Noise Analysis using a CCII∞ based structure"
Thomas Noulis, Stylianos Siskos, Laurent Bary and Gerard Sarrabayrouse | M1B Session: Digital Architecture design
Chair: Cristina Silvano, Politecnico di Milano, Italy M1B-1: "Parallelized Booth-Encoded Radix-4 Montgomery Multipliers"
Nathaniel Pinckney, Philip Amberg and David Harris
M1B-2: "Dual-Field Arithmetic Core for High-Performance Cryptographic
Operations"
Alessandro Cilardo, Roberta Piscitelli, Nicola Mazzocca and Nicola Petra
M1B-3: "On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters"
Gian Carlo Cardarilli, Alberto Nannarelli and Marco Re
M1B-4: "A Segmented High-Speed Counter Based on the Use of Redundant Bits"
Athanasios Kakarountas, George Theodoridis, Harris Michail and Costas Goutis |
12:00-13:30 | Lunch |
13:30-15:00 | Lecture Room 1 | Lecture Room 2 |
| M2A: Special Session: "3D integration: how far are we from the next leap forward in system integration?"
Co-Chairs: Trevor Karlson, IMEC, Belgium, Antonis Papanikolaou, IMEC, Belgium
M2A-1: "3D-SIC Pursuing Moore’s Law Momentum besides and beyond Transistor Scaling: A Case-Study"
Paul Marchal, Antonis Papanikolaou, Michele Stucchi, Katti Guruprasad, Diederik Verkest, Bart Swinnen, Eric Beyne
M2A-2: "3D Capacitive Coupling Interconnections for High Bandwidth Data Communication"
Roberto Canegallo, Luca Ciccarelli, Federico Natali, Alberto Fazzi
M2A-3: "3D Design Challenges - from WLB to PoP"
Jochen Reisinger | M2B Session: DSP Implementations Chair: Sergio Bampi, UFRGS, Brazil M2B-1: "A hardware module for automatic exposure correction in real-time video systems"
Chryssanthi Iakovidou, Vassilios Vonikakis and Ioannis Andreadis
M2B-2: "A Lifting-Based DWT and IDWT Processor with Support for Higher Order Wavelet Filters"
Andre Guntoro and Manfred Glesner
M2B-3: "Hardware Implementations of Membership Function Generators for Fuzzy Systems"
Angelos Amanatiadis, Georgios Sirakoulis and Ioannis Andreadis
M2B-4: "A Fast Converging High Throughput LDPC Decoder FPGA Implementation"
Kuo-Hsing Juan, Mong-kai Ku and Yu-min Chang |
15:00-16:00 | Coffee Break Poster Area
M1 POSTER SESSION
Chair: Konstantinos Tatas, Frederick University, Cyprus
M1-1: "A Fully CMOS-Compatible Optical H-Tree & Clock Recovery System"
Charles Thangaraj and Tom Chen
M1-2: "A Meta-heuristic for Shared BDD Minimization"
Sezer Goren
M1-3: "Layout verification for mm-wave wireless IC design"
James Howarth, Neil Weste and Jeffrey Harrison
M1-4: "Property Checking with Constraint Integer Programming"
Tobias Achterberg, Markus Wedler and Raik Brinkmann
M1-5: "Via-Aware Clock Distribution Network"
Ali Mohammadi Farhangi and Asim Javad Al-Khalili
M1-6: "An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits"
Cristiano Lazzari, Thiago Assis, Fernanda Kastensmidt, Gilson Wirth, Ricardo Reis and Lorena Anghel
M1-7: "Chip Level Testing for Core based SOC designs"
Tarun Aggarwal, Arijit Mukhopadhyay
M1-8: "Circuit Reduction Method Related to the Multi-port Circuit Synthesis"
Goro Suzuki and Kosuke Saiki
M1-9: " ILDJIT: a parallel dynamic compiler”
Simone Campanoni, Giovanni Agosta and Stefano Crespi Reghizzi
M1-10: "Improving resource utilization under EDF-based mixed scheduling in multiprocessors real-time systems"
BHATTI Muhammad Khurram, MUHAMMAD Farooq, BELLEUDY Cécile and Auguin Michel
M1-11: "Task Scheduling and Allocation for A Peak Power Control in The Multi-core System"
Sunghwan Park, Jaehwan Kim, Iljong Jung, Seokhee Lee, Kiseok Chung and Jongwha Chong
M1-12: "Trade-offs for High Yield in 90 nm Subthreshold Floating-gate Circuits by Monte Carlo Simulations"
Jon Alfredsson and Snorre Aunet
M1-13: "A Flexible Simulation Framework for Reconfigurable Processors"
Nikolaos Vassiliadis, George Theodoridis and Spiridon Nikolaidis
M1-14: "Improving Mixed-Signal Verification by Assertion Based Design"
Stefan Laemmermann, Alexander Pacholik, Alexander Jesser, Roland Weiss, Juergen Ruf, Wolfgang Fengler, Lars Hedrich, Thomas Kropf and Wolfgang Rosenstiel
M1-15: "An Energy Aware CMOS Front End for 2.4 GHz ISM Band Low Power Applications"
Aaron Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo and Alper Cabuk
M1-16: "Assertion Based Functional Verification of Multiple-Clock GALS Systems"
Rostislav Dobkin, Tsachy Kapshitz, Shaked Flur and Ran Ginosar
M1-17: "OFDM Datapath Baseband Processor for 1 Gbps Datarate"
Milos Krstic, Maxim Piz, Marcus Ehrig and Eckhard Grass
M1-18: "Cproc: An efficient Cryptographic Coprocessor"
Dimitris Theodoroupolos, Ioannis Papaefstathiou and Dionisios Pnevmatikatos
M1-19: "SSTA with correlations considering input slope and output load variations"
Zeqin Wu, Philippe Maurine, Gilles Ducharme and Nadine Azemard-Crestani
M1-20: "A Embedded Readout System for Capacitive Sensor Arrays"
Spyros Pavlos, Eystahios Kyriakis-Bitzaros and Stavros Chatzandroulis
M1-21: "Optimization of RNS FIR Filters for 6-inputs LUT Based FPGAs"
Gian Carlo Cardarilli, Marco Re, Adelio Salsano and Salvatore Pontarelli |
16:00-17:30 | Lecture Room 1 | Lecture Room 2 |
| M3A Session: Physical Design
Chair: Costas Goutis, Univ. of Patras, Greece M3A-1: "Multi-Clustering Net Model for Placement Algorithms"
Andrey Ziyatdinov, David Baneres and Jordi Cortadella
M3A-2:"Impact of Fill Pattern on RF Response of Passive Elements"
Artur Balasinski
M3A-3:"Statistical sizing methodology of an SRAM in presence of signal races and variability conditions"
Michael Yap-San-Min, Philippe Maurine and Michel Robert
M3A-4:"Power Saving in CMOS Processors by Optimal Wire Spacing"
Konstantin Moiseev, Shmuel Wimer and Avinoam Kolodny | M3B Session: Building Blocks for Embedded Systems Chair: Michel Robert, LIRMM, France
M3B-1: "Profile-based Workload Prediction Method for Dynamic Voltage and Frequency Scaling in Multiprocessor Embedded System"
Seungyong Oh, Jungsu Kim, Sungpack Hong, Sungjoo Yoo and Chong-Min Kyung
M3B-2:"An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks"
Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria and Cristina Silvano
M3B-3:"Design of Low Power Pulse UWB Transceiver"
Mengmeng Liu, Sheng Zhang, Shuo Wang, Jianliang Zhang and Runde Zhou
M3B-4:"Performance Analysis of Soft and Hard Single-Hop and Multi-Hop Circuit Switched Interconnects for FPGAs"
Jae Young Hur, Kees Goossens and Lotfi Mhamdi |
| | | |
Tuesday, October 14, 2008 |
8:00-9:00 | Registration |
9:00-10:00 | Keynote Talk: “Design and Programming strategies for MPSoC”
Dr. Ahmed Jerraya, CEA-LETI, MINATEC, France |
10:00-10:30 | Coffee Break |
10:30-12:00 | Lecture Room 1 | Lecture Room 2 |
| T1A Special Session: "Subthreshold Architectures and Circuits" Chair: Prof. Yusuf Leblebici, EPFL, Switzerland
T1A-1: “Process-Adaptive Digital Sub-threshold Logic & Memory”
Kaushik Roy, Jaydeep P. Kulkarni, and Myeong-Eun Hwang
T1A-2: “Circuit Techniques to Reduce the Supply Voltage Limit of Subthreshold MCML Circuits”
Massimo Alioto, Yusuf Leblebici,
T1A-3: “Adaptive Vgs: A Novel Technique for Controlling Power and Delay of Logic Gates in Sub-VT Regime”
B. Kheradmand Boroujeni, C. Piguet, Yusuf Leblebici,
T1A-4:"Pico-Watt Source-Coupled Logic Circuits”
Armin Tajalli, Yusuf Leblebici, Elizabeth J. Brauer
| T1B Session: Embedded Systems: Memory exploration and optimization Chair: David Atienza,Universidad Compultense de Madrid, Spain
T1B-1: "Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems"
Nikolaos Kroupis and Dimitrios Soudris
T1B-2: "Automatic Synthesis of Design Alternatives for Fast Stream-Based Out-of-Order Communication"
Joachim Keinert, Christian Haubelt and Jürgen Teich
T1B-3: "A Scratch-Pad Memory Accelerator for Exploiting Run-Time Reuse"
Athanasios Milidonis, Vasileios Porpodas, Nikolaos Alachiotis, Athanasios Kakaroudas, Harris Michail, George Panagiotakopoulos and Costas Goutis
T1B-4: "Systematic Evaluation of Dynamic Data Structures in Network Applications"
Ioannis Iosifidis, Christos Baloukas, Alexandros Bartzas, Dimitrios Soudris, Konstantinos Potamianos and Nikolaos Voros |
12:00-13:30 | Lunch |
13:30-15:00 | Lecture Room 1 | Lecture Room 2 |
| T2A New Devices and Modeling Chair: Salvador Mir, TIMA Labs, France
T2A-1: "Design of a Family of Gate-level Reconfigurable Logic Cells Based on Double-Gate MOSFETs"
Ilham Hassoune, Ian O'Connor and David Navarro
T2A-2: "Dynamically reconfigurable CNTFET logic cell matrix programming methods"
Junchen Liu, Ian O'Connor, David Navarro and Frédéric Gaffiot
T2A-3: "Pseudo Floating-Gate Design Limitations in Nano-CMOS with Low Power Supply"
Jon Alfredsson and Snorre Aunet
T2A-4: "A New Method for Calculating Resistive Losses on Lightly and Heavily Doped Substrates"
Yiorgos Bontzios and Alkis Hatzopoulos | T2B Session: Reconfigurable Systems Chair: Flávio Rech Wagner, UFRGS, Brazil
T2B-1: "A Novel Algorithm for Temperature-Aware P&R on 3D FPGAs"
Kostas Siozios and Dimitrios Soudris
T2B-2:" A Novel Cluster-based Logic Block with Variable Grain Logic Cells author"
Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga,Motoki Amagasaki, Masahiro Iida and Toshinori Sueyoshi
T2B-3:"A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication"
Vincenzo Rana, David Atienza, Marco Domenico Santambrogio, Donatella Sciuto and Giovanni De Micheli
T2B-4: "Embedding High Performance Multipliers in Coarse Grain Reconfigurable Array
Architectures"
Grigoris Dimitroulakos, Stavros Georgiopoulos, Nikos Kostaras and Costas Goutis |
15:00-16:00 | Coffee Break Poster Area
T1 Poster Session: Ph.D. Forum
Chair: George Theodoridis, Aristotle Univ. of Thessaloniki, Greece T1-1: "Design and study of integrated circuits for high frequency applications"
Vasilis Kalenteridis and Siskos Stylianos
T1-2: “Tight Integration in Physical Synthesis”
Glauco Borges Valim dos Santos, Marcelo de Oliveira Johann and Ricardo Augusto da Luz Reis
T1-3: “Efficient Hardware Architectures for H.264 Video Encoding and Decoding”
Vagner S. Rosa and Sergio Bampi
T1-4: “Data Structures Optimization Methodology of Dynamic Applications in Embedded Systems”
Christos Baloukas and Dimitrios Soudris
T1-5: “Extraction and Utilization of Software Metadata for Dynamic Embedded Applications”
Alexandros Bartzas and Dimitrios Soudris
T1-6: “Efficient Folded Programmable FIR Filter Schemes based on High-Performance Array Multipliers”
Dimitris Bekiaris and Kiamal Pekmestzi
T1-7: “Real-Time Stereo Vision Techniques”
Christos Georgoulas and Ioannis Andreadis
T1-8: “A Hardware and Software Design Approach for Designing Performance and Energy Efficient Reconfigurable Architectures”
Kostas Siozios and Dimitrios Soudris
T1-9: “Prediction of Design Errors using Revision History Information”
Jose Augusto Nacif and Antonio Otavio Fernandes
T1-10: “A Methodology for the Design and Simulation of Datapath Applications”
Laura Frigerio and Fabio Salice |
16:00-17:30 | Lecture Room 1 | Lecture Room 2 |
| T3A Special Session: European-funded Research and Development: Present and Future Co-Chairs: Georgi Kuzmanov, Technical University of Delft, The Netherlands and D. Soudris, Democritus Univ. of Thrace, Greece
T3A-1: “European research in FP7-ICT: 2009-2010 outlook” Panagiotis Tsarchopoulos, Unit G3 - Embedded systems, EU Commission, Belgium (Invited Speaker)
T3A-2: “MORPHEUS – Heterogeneous Reconfigurable SOC”
Alberto Rosti, Philippe Bonnot, Stelios Perissakis, Konstantinos Potamianos, and Wolfram Putzke-Röming
T3A-3: “MNEMEE: Memory management technology for adaptive and efficient design of embedded systems”
Stylianos Mamagkakis, Peter Lemmens, Dimitrios Soudris, Twan Basten, Peter Marwedel, Dimitrios Kritharidis and Gwenael Guilmin
T3A-4: “MOSART: Mapping Optimisation for Scalable multi-core ARchiTecture
Bernard Candaele, Axel Jantsch, Tom Ashby, Kari Tiensyrjä, Frank Ieromnimon, Bart Vanthournout, Philippe Di Crescenzo, Dimitrios Soudris T3A-5: “Corallia Clusters Initiative”, Jorge-A. Sanchez-P., Corallia, Greece | T3B Session: CAD Tools Chair: Avinoam Kolodny, Technion Institute, Israel T3B-1: "Universal Methodology to Handle Differential Pairs During Pin Assignment"
Tilo Meister, Jens Lienig and Gisbert Thomke
T3B-2: "An Approximation Algorithm for Generalized EXOR Projected Sum of Products"
Anna Bernasconi, Valentina Ciriani and Roberto Cordone
T3B-3: "A method and tool for early design/technology search-space exploration for 3D ICs"
Kostas Siozios, Antonis Papanikolaou and Dimitrios Soudris
T3B-4: "Timed Coloured Petri Nets for Performance Evaluation of DSP Applications"
Laura Frigerio, Kellie Marks and Argy Krikelis |
Wednesday, October 15, 2008 |
9:00-10:00 | Keynote Talk: “CLEAN: Leakage Aware Design for Next Generation's SOCs”
Dr. Ing. Roberto Zafalon,
STMicroelectronics Agrate Brianza (MILANO), Italy |
10:00-10:30 | Coffee Break |
10:30-12:00 | Lecture Room 1 | Lecture Room 2 |
| W1A: Special Session: Wearable Electronics
Chairs: Annalisa Bonfiglio, University of Cagliari, Italy W1A-1:"Wearable Motion Capture Devices Based on Smart Textile Technology"
Alessandro Tognetti, Gaetano Anania, Nicola Carbonaro, Fabrizio Cutolo, Gabriele Dalle Mura, Mario Tesconi, Giuseppe Zupone, Danilo De Rossi
W1A-2:"Wearable Devices for Real Time Monitoring of Emergency Operators"
Giannicola Loriga, Gabriela Dudnik, Rita Paradiso, Guy Voirin, Jean Luprano,
W1A-3:"Wearable SoC UWB (3.1-10.6 GHz) Radar for Cardiopulmonary Monitoring" Domenico Zito, Domenico Pepe, Fabio Zito, Martina Mincica | W1B: Video processing
Chair: Odysseas Koufopavlou, Univ. of Patras, Greece
W1B-1: "SystemC Modeling of an H.264/AVC Intra Frame Encoder Architecture"
Bruno Zatt, Cláudio Diniz, Luciano Agostini, Altamiro Susin and Sergio Bampi W1B-2: "Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC"
Yibo FAN, Takeshi IKENAGA and Satoshi GOTO
W1B-3: "Architectural Design for Forward and Inverse Transforms of H.264/AVC Standard Focusing in the Intra Frame Coder"
Felipe Sampaio, Fabiane Rediess, Carolina Fonseca, Sergio Bampi, Altamiro Susin and Luciano Agostini
W1B-4: "A Dynamically Reconfigurable Motion Estimation IP Core for Adaptive Multimedia Systems"
Konstantinos Tatas and Dimitrios Soudris |
12:00-13:30 | Lunch |
13:30-15:00 | Lecture Room 1 | Lecture Room 2 |
| W2A Session: New Devices for bioapplications
Chair: Stelios Siskos, Aristotle Univ. of Thessaloniki, Greece W2A-1: "A 50 uW low-voltage CMOS Biopotentiostat for low-frequency Capacitive Biosensor"
Jordi Colomer, Pere Miribel-Català, Albert Saiz-Vela, Manel Puig-Vidal, Josep Samitier and Abdelhamid Errachid
W2A-2: "Integrated planar micro-coil for trapping biological species in a lab-on-chip microsystem"
Christophe Escriba, Rémy Fulcrand, Philippe Artillan, Lin Gao, Bruno Estibal, Ali Boukabache, Anne Marie Gue and Jean-Yves Fourniols
W2A-3: "Placement-Aware Architectural Synthesis of Digital Microfluidic Biochips using ILP"
Elena Maftei, Paul Pop, Jan Madsen and Thomas Stidsen
W2A-4: "Multi-site nerve cuff based implantable system for wide bandwidth ENG signal recording"
Xianhong Xu, John Taylor and Chris Clarke | W2B Session: Digital Architecture design
Chair: Costas Goutis, Univ. of Patras, Greece W2B-1: "The ByoRISC configurable processor family"
Nikolaos Kavvadias and Spiridon Nikolaidis
W2B-2:"Assertion based fault-tolerant processor: How to recover from design errors"
Thiago Nunes Coelho Cardoso, Celina Gomes do Val, José Augusto Nacif, Antônio Otávio Fernandes and Claudionor Nunes Coelho Jr.
W2B-3:"Analysis and Improvement of SER Immunity of Combinational Logic"
Tsau-Shuan Wu, Cengiz Alkan and Tom Chen
W2B-4: "A Synthesis Postprocessor for Fully Morphable RTL Datapaths"
George Economakos and Sotiris Xydis
|
15:00-16:00 | Coffee Break Poster Area
W1 Poster Session
Chair: George Economakos, NTUA, Greece W1-1: "Standard-Logic Quasi Delay Insensitive Registers"
Eslam Yahya, Marc Renaudin and Gregory Lopin
W1-2: "Transient Response in MOBILE-based Circuits"
José M. Quintana and María J. Avedillo
W1-3: "An Ultra Low Power 5.2 GHz True Single Phase Clock CMOS Prescaler"
Vamshi Krishna, Do Manh Anh, Yeo Kiat Seng and Boon Chirn Chye
W1-4: "High Performance ASIC Implementation of the SNOW 3G Stream Cipher"
Paris Kitsos, George Selimis and Odysseas Koufopavlou
W1-5: "High Performance Hardware Architectures for a Hexagon-Based Motion Estimation Algorithm"
Ozgur Tasdizen, Abdulkadir Akin, Halil Kukner, Ilker Hamzaoglu and Fatih Ugurdag
W1-6: "Low Power IEEE 802.11n LDPC Decoder Hardware"
Merve Peyic, Hakan Baba, Ilker Hamzaoglu and Mehmet Keskinoz
W1-7: "Energy Minimization with Bank-Type Assignment for Heterogeneous Multi-Bank Memory"
Meikang Qiu and Edwin Sha
W1-8: "A Low-Voltage Current-Mode Single Input Multiple Output Universal Biquad Filter"
Costas Laoudias and Costas Psychalinos
W1-9: "Joint Exploitation of Horizontal/Vertical Parallelism and Operation Chaining for Flexible DSP Synthesis"
Sotiris Xydis, George Economakos, Dimitrios Soudris and Kiamal Pekmestzi
W1-10: "A Step Beyond TLM Inferring Architectural Transactions at Functional Untimed Level"
Sandro Penolazzi, Mohammad Badawi and Ahmed Hemani
W1-11: "A Software Controllable Variable Line Size Cache Exploiting High On-Chip Memory Bandwidth for Low Power Embeded SoCs"
Takatsugu Ono, Koji Inoue, Kazuaki Murakami and Kenji Yoshida
W1-12: "Numerical Method for Modeling Process Variations and NBTI"
Lucas Brusamarello, Gilson Wirth, Vinicius Camargo, Mauricio da Silva, Roberto da Silva and Peter Glosekotter
W1-13: "A Novel Hardware Architecture Dedicated to Binary Arithmetic Decoder Engines for the H.264/AVC CABAD"
Dieison Antonello Deprá, Vagner Santos da Rosa and Sergio Bampi
W1-14: "An Electronic System-Level Design Methodology with a Motion-JPEG Encoder Case Study"
Jan Kai-Yuan, Hsu Sheng-Tsung and Lin Youn-Long
W1-15: "Physical Design for Reduced Delay Uncertainty in High Performance Clock Distribution Networks"
Dimitrios Velenis, Marios Papaefthymiou and Eby G. Friedman
W1-16: "An Efficient Design of Parallel Loading Shift Register Using Reversible Flip-Flops"
Ashis Kumer Biswas, Lafifa Jamal and Hafiz Md. Hasan Babu
W1-17: "A generic platform for the SoC implementation of grammar-based applications"
Alexandros Dimopoulos, Christos Pavlatos, Panagiota Karanasou and George Papakonstantinou
W1-18: "Mitigating Performance Loss in Aggressive DVS Using Dual-Sensing Flip-Flops"
Yuji Kunitake, Toshinori Sato and Hiroto Yasuura
W1-19: "Ultra Low Voltage High Speed NAND and NOR logic"
Omid Mirmotahari and Yngvar Berg
W1-20: "FPGA Leakage Power Reduction Using CLB-Clustering Technique"
Mohammad Mehdi Tohidi and Nasser Masoumi
W1-21: "Hyper-Rings: A Cost Effective Improvement of the Hierarchical Rings for Network-on-Chip"
Stephan Bourduas |
16:00-17:30 | Lecture Room 1 | Lecture Room 2 |
| W3A Session: Testing
Chair: K. Pekmestzi, NTUA, Athens W3A-1: X-Eliminator: "A Technique to Mask All Unknown Responses with No Test Loss and Minimized Masking Data Overhead"
Youhua Shi, Nozomu Togawa, Masao Yanagisawa and Tatsuo Ohtsuki
W3A-2:"The Time Dilation Scan Architecture for Timing Error Detection and Correction"
Andreas Floros, Yiorgos Tsiatouhas and Xrysovalantis Kavousianos
W3A-3:"Non-redundant Scheme for Arbitrary Error Detection in Combinational Circuits"
Osnat Keren, Ilya Levin and Mark Karpovsky
W3A-4:"A Concurrent BIST scheme exploiting dont care values"
Ioannis Voyiatzis, Dimitris Gizopoulos and Antonis Paschalis | W3B Session: Low Power Design
Chair: Nadine Azemard, LIRMM, France W3B-1: "Comparison of Two Autonomous AC DC Converters for Piezoelectric Energy Scavenging Systems"
Enrico Dallago, Daniele Miatton, Giuseppe Venchi, Valeria Bottarel, Giovanni Frattini, Giulio Ricotti and Monica Schipani
W3B-2: "An Enhanced Low-Power Precomputation-Based Content-Addressable Memory" Architecture Sebastian Ang, Chin-Hung Peng, Jürgen Kemper, Uwe Schwiegelshohn and Feipei Lai
W3B-3: "Application Specific Shifted-Gray-Code Encoding for Instruction Memory Address Bus Switching Reduction"
Hui Guo
W3B-4: "Sub-Threshold Leakage Reduction of Asynchronous Pipelines Using Dependency-Graph Abstract Model"
Behnam Ghavami and Hossein Pedram |
