Architectures and Methodologies for Dynamic REconfigurable Logic
The main objective of the proposed project is to develop methodologies, tools and intellectual property blocks to be integrated in a mixed granularity dynamically reconfigurable System-on-Chip (SoC) implementation platform for the efficient realization of wireless communications systems. The proposed methodology, tools, reusable intellectual property blocks and the mixed granularity reconfigurable implementation platform will be used for the development of systems from the wireless communication domain including critical parts of a wireless LAN system (e.g. HIPERLAN/2, IEEE 802.11a) and a multimedia processor for wireless terminals. This will be an additional contribution of the proposal.
The use of the introduced methodologies, tools, reusable intellectual property blocks and the mixed granularity reconfigurable implementation platform is expected to lead to largely improved quality in terms of different features and to increased competitiveness of European telecom system manufacturers mainly in the domain of wireless communications. The major improvements will concern: a) the reduced design time and time to market of systems in the target application domain and b) the improved balance between flexibility (highly desired in the target application domain) and performance, energy and area in comparison to traditional implementation platforms such as custom (hardware) and instruction set (software) processors and to more recent single granularity reconfigurable ones such as Field Programmable Gate Arrays (FPGAs).
Partners in this project are Intracom, STMicroelectronics Belgium (former AME), Democritus University of Thrace, and IMEC.